1. Field of the Invention
The present invention relates to a dummy pattern arrangement apparatus, and more specifically, to a dummy pattern arrangement apparatus used in a design process of a semiconductor integrated circuit.
2. Description of Related Art
In designing of a layout of a semiconductor device, data for forming dummy pattern is created. The meaning of the dummy pattern will be described before explaining embodiments of the present invention. FIGS. 1A, 1B, and 1C are diagrams for explaining significances of the dummy pattern.
FIG. 1A shows a layout of a common MOS (Metal-Oxide-Semiconductor) transistor.
An area 101 includes a gate 102 and a diffusion layer 103. The area 101 is an area in which the finished shape of the gate 102 and the diffusion layer 103 which form an element is required to be formed in high precision. In the following, such an area 101 is designated as the area A. Here, the area A is supposed to be a rectangle form, unless it is mentioned otherwise specially.
FIG. 1B shows a plan view after formation of an element.
As finer microfabrication proceeds, it becomes more difficult to attain uniform manufacturing accuracy. An area A 104 that is a portion corresponding to the area A after the diffusion process becomes a gate 105 and a diffusion layer 106 as shown in FIG. 1B, for example. In FIG. 1B, the finished shape of the diffusion layer 106 is smaller than the originally expected shape 107.
In order to flatten a surface, the surface is polished by the CMP (Chemical Mechanical Polishing) process. However, in order to suppress variations of the polished amount, it is required to suppress variation of data density of a portion corresponding to the area A.
For resolving the problem, a MOS transistor takes a configuration shown in FIG. 1C, for example.
As shown in this plan view FIG. 1C, pattern 111 for attaining uniformity of the density is arranged in a vicinity of a gate 109 and a diffusion layer 110 in design in an area A 108 that is a portion corresponding to the area A. In this case, the pattern 111 is a pattern consisting of a plurality of pattern elements arranged in a grid formation and formed in a same process as the diffusion layer 110.
Similarly, also in the gate process, etching amount varies by ununiformity of data density, which brings a problem that the formed element does not have the desired shape. Therefore, similarly to the diffusion layer case, it is required to arrange pattern for attaining the uniformity of the density.
Here, a shaped pattern which does not function as a part of a circuit component like an electronic elements or wiring and is arranged optionally in a portion where the data density is coarse is called as a “dummy pattern.” The pattern 111 is a dummy pattern.
An EB operation is known as a technique used in arranging the dummy pattern.
In the EB operation, EB data (Electron Beam Exposure Data or Electron-Beam Lithography Data) is created. For example, the EB data for producing a photomask of an LSI (Large Scale Integration) is created by converting the layout data created by a designer with CAD (Computer Aided Design).
FIG. 2 is a plan view for explaining a starting point of the dummy pattern arrangement in the case of using a common EB operation.
In a common EB operation, for generating dummy pattern on a predetermined area A 201, the starting point of the dummy pattern creation is commonly set at the lower-left point 202 shown in FIG. 2.
FIG. 3 shows a common method of layout-arrangement of a dummy pattern in the EB operation.
Generally, after arranging elements 301 required for functions of the product, dummy patterns 302 that are formed in a same processing layer by a program used finally at the time of EB shipment are arranged in a gap area. A gap area means that any circuit element or interconnection is not formed on the area, namely, the area is an empty or blank space on a chip area. Here, the program used at the time of the EB shipment is called as the EB operation.
Processing in the EB operation is usually performed as follows.    (1) An X-direction size 303 and a Y-direction size 304 of each dummy pattern are specified. Each dummy pattern element composing the dummy pattern 302 shows a shape with specified sizes.    (2) A lower-left point 305 of the data indicating a region on which dummy pattern is arranged is set to a starting point, and the X-direction arrangement gap 306 and the Y-direction arrangement gap 307 between adjacent dummy pattern elements are specified.    (3) Each dummy pattern element keeps a certain gap 308 to a shaped pattern forming an element, and also keeps a certain gap to an element 301. On a region where such a gap cannot be kept, no dummy pattern element is generated.
FIG. 4A is a layout flow that adopts a dummy pattern arrangement method in a common EB operation. Hereafter, this layout flow is called as a related technique 1.
(1) Step S401
Circuit information for forming discrete components is referred to.
(2) Step S402
The discrete component data is formed based on the circuit information for creating the discrete components.
(3) Step S403
It is judged by checking whether there is any problem in the shapes of the discrete components. If there is any problem in the shapes of the discrete components, namely, the shapes of the discrete components do not satisfy a predetermined checking rule, the discrete component data are re-created. In the following, the representation “there is any problem,” “there is no problem” and the like are used in this meaning.
(4) Step S404
If it is judged that there is no problem in the shapes of the discrete components, the circuit information for creating a functional block is referred to.
(5) Step S405
In a functional block data creation process, the functional block data is created based on the circuit information for creating the functional block.
(6) Step S406
Regarding the created functional block data, it is judged by checking whether there is any problem in the shape of the functional block. If there is any problem in the shape of the functional block, the flow returns to the functional block data creation process, and the functional block data is re-created.
(7) Step S407
If there is no problem in the shape of the functional block, the circuit information for creating a 1-chip layout is referred to.
(8) Step S408
In a 1-chip layout process, the data of 1-chip layout is created based on the circuit information for creating the 1-chip layout.
(9) Step S409
Regarding the created data of 1-chip layout, it is judged by checking whether there is any problem in the shape of the 1-chip layout is performed. If there is any problem in the shape of the 1-chip layout, the flow returns to the 1-chip layout process, and the data of 1-chip layout is re-created.
(10) Step S410
If there is no problem in the shape of the 1-chip layout, the GDS data to EB data conversion process is performed, in which the GDS (General Data Stream) data is converted into the EB data.
(11) Step S411
Information of a specification of dummy pattern arrangement is referred to.
(12) Step S412
A dummy pattern arrangement process is performed to the data obtained in the GDS data to EB data conversion process. In this process, the dummy pattern is arranged based on the information of the specification of dummy pattern arrangement.
(13) Step S413
Regarding the created data of dummy pattern arrangement, it is judged by checking whether there is any problem in the shape of the dummy pattern. If there is a problem in the shape of the dummy pattern, the flow returns to the GDS data to EB data conversion process, where the conversion processing is redone and the dummy pattern is rearranged similarly with the above-mentioned processing.
(14) Step S414
If there is no problem in the shape of the dummy pattern, the created data as the result of above processing is shipped as the EB data in the EB shipment process.
FIG. 4B is a layout flow of a method different from the related technique 1. Hereinafter, this method is called as a related technique 2.
The related technique 2 is different from the related technique 1 in a check process of the 1-chip layout. Specifically, the dummy pattern arrangement process and the GDS data to EB data conversion process are interchanged in order. Therefore, the processing of the steps until the step S408 is performed similarly with the related technique 1 shown in FIG. 4A. After the step S408, the step S415 and thereafter explained below are performed in the related technique 2.
(15) Step S415
The 1-chip layout check is performed. A flow to step S415 is the same as those of steps S401 to S408 of FIG. 4A.
(16) Step S416
A specification of dummy pattern arrangement is referred to after the 1-chip layout check.
(17) Step S417
In the dummy pattern arrangement process, the dummy patterns are arranged based on the specification of dummy pattern arrangement.
(18) Step S418
Next, the processing of converting GDS data which is a result of the foregoing processes into EB data is performed at the GDS data to EB data conversion process.
(19) Step S419
It is judged by checking whether there is any problem in the shape of the dummy patterns. If there is any problem in the shape of the dummy pattern, the flow returns to the dummy pattern arrangement process, where the dummy pattern is rearranged similarly to the above-mentioned processing.
(20) Step S420
If there is no problem in the shape of the dummy pattern, the created data as the result of above processing is shipped as the EB data in the EB data shipment process.
In the following, an explanation is given based on the processing shown in the flow of FIG. 4A.
In the above mentioned explanation of related techniques, the variation of density is suppressed in a certain level, although the dummy pattern arrangement is roughly determined. However, in recent years, microfabrication of pattern has proceeded into even finer, and higher precision in finished products is required. Moreover, since the finished shape of an element depends on the shape of the dummy pattern around the element, also for the dummy pattern arrangement, a specification considering the required finished precision has become sought.
However, when an identical performance is required for each of the patterns having a same shape, if the shapes of the dummy patterns that is respectively arranged in the vicinity of the elements with the same shape is different from one another, the finished shapes of the elements will be different and they cannot exhibit a same transistor characteristic. Therefore, it is required to arrange dummy patterns with an identical shape in the vicinity of respective elements that are required to have an identical shape and high precision.
As shown in FIG. 5, designating the vicinity of each of elements (an element 502 and an element 503) having a same shape in a chip area 501 as the area A (an area A 504 and an area A 505), it is required for the dummy patterns with the identical shape to be arranged in the respective areas A (the area A 504 and the area A 505).
At this time, the sizes of the area A 504 and the area A 505 that are the areas A are the same. Moreover, arrangement orientations of the element 502 and the element 503 in the respective areas A are the same.
When the layout flow (the related technique 1 of FIG. 4A) adopting a dummy pattern arrangement in a common EB operation is performed, the starting point of the dummy pattern creation is fixed to the lower-left point 506 of the respective area in which the dummy patterns are to be created.
When more than two areas (the area A 504 and the area A 505) in which dummy patterns are to be created respectively exist in a chip area 501, since the dummy pattern creation starting point is set to the lower-left point 506 of the chip area, and the dummy pattern is created for the whole surface of the chip area 501, the relations between the respective areas A (the area A 504 and the area A 505) and the dummy pattern creation starting point become different, and the arrangement of the dummy patterns in respective areas A are no longer the identical shape. Therefore, the dummy patterns arranged in the respective vicinities of elements 502 and 503 do not have a same arrangement.
Referring to FIG. 6, this problem is explained in detail in the case that the layout flow of the related technique 1 is executed.
The chip area 600 corresponds to the chip area 501 in FIG. 5. The diffusion layer 601 and the gate 602 correspond to the element 502 shown in FIG. 5. The diffusion layer 603 and the gate 604 correspond to the element 503 shown in FIG. 5. The diffusion layer 601 and the diffusion layer 603 are formed in the same process as the dummy pattern 605.
In the vicinity of the element 502, the gaps between the dummy pattern and the element 502 are shown in FIG. 6 as the gap 606 and the gap 607. Note here that since the locations of the dummy patterns are determined on the basis of the creation starting point 506 shown in FIG. 5, the dummy pattern arrangement in the vicinity of the element 503 can be different from that of in the vicinity of the element 502.
For example, in the vicinity of the element 503, the gaps 608, 609 between the dummy pattern and the element 503 are shown in FIG. 6, which is different from the gaps 606, 607 in the vicinity of the element 502. As shown in this case, the dummy pattern arrangements in the vicinity of the element 502 and the element 503 existing in the area A 504 and the area A 505 shown in FIG. 5, respectively, can be different from each other. Therefore, a finished shape of the element existing in each area can be different from each other, and it becomes difficult to expect a same transistor characteristic between them.
FIG. 7 shows a plan view of a layout in the case where the orientation of an area A is different from that of another area A. A chip area 701 shows an area on a chip. A lower-left point 702 is the dummy pattern creation starting point. An area A 703 and an area A 704 show dummy pattern creation areas A. An element 705 and an element 706 show elements to be formed on respective dummy pattern creation areas A. In an example shown in FIG. 7, a dummy pattern creation area A and another dummy pattern creation area A have a same shape and arranged in orientations different from each other by 90°.
FIG. 8 shows a layout showing relations between elements existing in a dummy pattern creation area A and the dummy patterns, from which a problem similar to the above-mentioned case regarding FIG. 6 occurs. The chip area 800 corresponds to the chip area 701 in FIG. 7. As shown in FIG. 7, a first area A and a second area A which have same shape are arranged in respective orientations different from one another by 90° on a chip. The relations between elements in dummy pattern creation areas A and the dummy patterns created thereon of the first and second areas A are as follows. In the first area, the gaps between “a diffusion layer 802 and a gate 803 which correspond to the element 705 of FIG. 7” and a “nearest dummy pattern among dummy patterns 805 arranged in the vicinity” are shown in FIG. 8 as the gaps 801, 804. In the second area, the gaps between “a diffusion layer 807 and a gate 808 which correspond to the element 706 of FIG. 7” and “the nearest dummy pattern among dummy patterns 810 arranged in the vicinity” are shown in FIG. 8 as the gaps 806, 809, which are different from the gaps 801, 804 in the first area A. Similarly, an arrangement relation between an element and a dummy pattern existing in each area can be different from those of other areas.
For overcoming the above mentioned problem occurred in the related technique 1, the related technique 2 can be adopted as below.
FIGS. 9A and 9B show a layout flow of a related technique 2 in which “in order to make dummy patterns having a same shape in the areas A, the dummy patterns only in the areas A are created at a stage of layout formation and are arranged in the areas A.” This is referred to as the related technique 2 in the following.
(1) Step S901
Circuit information for forming discrete components is referred to.
(2) Step S902
The discrete component data is created based on the circuit information for creating the discrete components.
(3) Step S903
It is judged by checking whether there is any problem in the shape of the discrete components. If there is any problem in the shapes of the discrete components, the discrete component data are re-created.
(4) Step S904
If it is judged that there is no problem in the shapes of the discrete components, the circuit information for creating the functional block is referred to.
(5) Step S905
In a functional block data creation process, the functional block data is created based on the circuit information for creating the functional block.
(6) Step S906
Regarding the created functional block data, it is judged by checking whether there is any problem in the shape of the functional block. If there is any problem in the shape of the functional block, the flow returns to the functional block data creation process, and the functional block data is re-created.
(7) Step S907
If there is no problem in the shape of the functional block, information of the specification of dummy pattern arrangement in a specific area is referred to.
(8) Step S908
In a dummy pattern arrangement process, the dummy pattern is arranged in the data processed in the functional block data creation process based on the information of the specification of dummy pattern arrangement of the specific area.
(9) Step S909
To the created dummy pattern arrangement, it is determined by checking whether there is any problem in the shape of the dummy pattern. If there is any problem in the shape of the dummy pattern, the flow returns to the GDS data to EB data conversion process, where the conversion processing is redone and the dummy pattern is rearranged similarly with the above-mentioned processing.
(10) Step S910
If there is no problem in the shape of the dummy pattern, the circuit information for creating the 1-chip layout will be referred to.
(11) Step S911
In the 1-chip layout process, a 1-chip layout is created based on the circuit information for creating the 1-chip layout.
(12) Step S912
To the created 1-chip layout, it is judged by checking whether there is any problem in the shape of the 1-chip layout. If there is any problem in the shape of the 1-chip layout, the flow returns to the 1-chip layout process, and the 1-chip layout will be re-created.
(13) Step S913
If there is no problem in the shape of the 1-chip layout, the conversion processing of converting the GDS data into the EB data will be performed in the GDS data to EB data conversion process.
(14) Step S914
The information of the specification of dummy pattern arrangement for non-specific area is referred to. The non-specific area means an area other than the previously mentioned specific area.
(15) Step S915
In a dummy pattern arrangement process, the dummy pattern is arranged in the data processed in the GDS data to EB data conversion process based on the information of the specification of dummy pattern arrangement for non-specific area.
(16) Step S916
To the created dummy pattern arrangement, it is judged by checking whether there is any problem in the shape of the dummy pattern. If there is any problem in the shape of the dummy pattern, the flow returns to the GDS data to EB data conversion process, where the conversion processing is redone and the dummy patterns are rearranged similarly with the above-mentioned processing.
(17) Step S917
If there is no problem in the shape of the dummy pattern, the created data as the result of above processing is shipped as the EB data in the EB data shipment process.
In the layout flow of a related technique shown in FIGS. 9A and 9B, a plurality of areas A are arranged on a various positions and orientations (namely, rotation angles) in the layout. The dummy patterns of the respective areas A are created so that the dummy pattern arrangements in respective areas A are same with each other. The step S907, step S908, and step S909 shown in FIGS. 9A and 9B (the dummy pattern arrangement process of a specific area after the functional block data creation process) are the processing stages for making the dummy pattern arrangements of the respective areas A to be same with each other. The dummy pattern arrangement for a portion other than the areas A is performed with the EB operation based on the specification for non-specific area dummy pattern arrangement, like processing stages of step S914 and step S915 shown in FIGS. 9A and 9B.
FIGS. 10A, 10B, 11A, 11B, 11C, 12A, and 12B are layout flows explaining the problems in the dummy pattern arrangement caused by the use of the related technique 2. FIGS. 10A, 10B, 11A, 11B, 11C, 12A, and 12B illustrate different problems, respectively. In these flow charts, the processing stages of step S901 to step S917 are common with those of FIGS. 9A, 9B.
Here, there are the following three problems.    Problem 1: The dummy pattern creation is performed each time the layout is corrected (FIGS. 10A and 10B).    Problem 2: The GDS data hierarchical structure is subjected to correction for the dummy pattern creation (FIGS. 11A, 11B, and 11C).    Problem 3: Since the dummy patterns are created on the GDS data, the amount of the GDS data being processed is large (FIGS. 12A and 12B).
These problems are explained below in detail.
Problem 1: “The dummy pattern creation is performed each time the layout is corrected.”
The problem 1 which occurs in the layout flow shown in the FIGS. 9A and 9B will be explained referring to FIGS. 10A and 10B.
In FIGS. 10A and 10B, the dummy pattern arrangement process (step S1001) and specification change (step S1002) are added comparing with the flow shown in FIGS. 9A and 9B. The dummy pattern arrangement process (step S1001) includes the dummy pattern arrangement process (step S908) and check process for checking the arranged dummy pattern (step S909). Specification change (step S1002) is performed to the circuit information that is referred to in a discrete component creation process (step S902) and the functional block data creation process (step S905). That is, the specification change is done when the circuit information is referred to at step S901 and step S904, or before the steps.
A dummy pattern is required to be arranged in a position where the dummy pattern and an element is not overlapped. Namely, a gap 308 is required to be kept between an element 301 and the dummy pattern, as explained in FIG. 3.
In the related technique 2 shown in FIGS. 10A and 10B, the dummy pattern is arranged after the layout of circuit components is created. Therefore, when a layout specification is changed, the dummy pattern on the area A is required to be re-created associated with this change, which requires a large amount of processing.
That is, after finishing the dummy pattern arrangement process (step S1001) shown in FIGS. 10A and 10B, if there occurs the specification change (step S1002) in the discrete component creation process (step S902) or the functional block data creation process (step S905), the shape of the element 301 changes.
To avoid this unintentional change of the element shape, it is also required to change the arrangement gap 308, and accordingly it becomes necessary to redo the dummy pattern arrangement process (step S908) and the check process (step S909) shown at step S1001.
Problem 2: “The GDS data hierarchical structure is subjected to correction for the dummy pattern creation.”
The problem 2 in the layout flow shown in the above-mentioned FIGS. 9A and 9B will be explained referring to the flow chart of FIGS. 11A and 11B and the layout arrangement shown in FIG. 11C.
The step S1101 shown in FIG. 11A is a cell-forming arrangement process of the dummy patterns that accompanies the data hierarchical structure correction. This cell-forming arrangement process is performed between the dummy pattern arrangement process (step S908) and the check process (step S909).
As shown in FIG. 11C, a 1-chip area (the chip area) 1100 includes a block B 1110, a block B 1120, and a block B 1130. The block B 1110 includes an area A 1111. The block B 1120 includes an area A 1121. The block B 1130 includes an area A 1131.
The block B 1110, the block B 1120, and the block B 1130 shown in FIG. 11C have a common configuration. An explanation will be given for a case where the area A 1111, the area A 1121, and the area A 1131 are formed to be a same shape.
In FIG. 11C, the areas A (the area A 1111, the area A 1121, and the area A 1131) are placed in the blocks B (the block B 1110, the block B 1120, and the block B 1130) respectively to construct a hierarchical structure. If a dummy pattern on the area A are kept to be arranged on the 1-chip area 1100 which is the top level of the layout hierarchical structure, the dummy patterns placed on the top hierarchy must be individually arranged on respective areas A (the area A 1111, the area A 1121, and the area A 1131) of the respective blocks B (the block B 1110, the block B 1120, the block B 1130).
In this case, for the block B in which the area A exists, it is generally more efficient to insert the dummy pattern for the area A. Therefore it is required to re-execute a dummy pattern cell-forming arrangement process (step S1101) associated with the correction of hierarchical structure level of data by which the dummy pattern is arranged on a hierarchical level of block B after the creation of the dummy data, and the subsequent processes. As a result, the amount of processing for correction and check increases.
In many cases, the data created in the discrete component creation process (step S902) or in the functional block data creation process (step S905) forms a cell. When the area A exists in this cell and a dummy pattern is required to be arranged in the area A, the correction of the hierarchical level of the dummy pattern and the subsequent processes are required.
Problem 3: “Since the dummy patterns are created on the GDS data, the amount of the GDS data being processed is large.”
The problem 3 which occurs in the layout flow shown in FIGS. 9A and 9B will be explained using FIGS. 12A and 12B.
In FIGS. 12A and 12B, a layout flow includes a circuit information reference process (step S901), a layout process (step S1201), an EB operation process (step S1202), and a shipment process (step S917). The “layout process (step S1201)” includes the “discrete component creation process (step S902)” to the “GDS data to EB data conversion process (step S913 (before conversion))”. The “EB operation process (step S1202)” includes the “GDS data to EB data conversion process (step S913 (after conversion))” to the “dummy pattern shape check process (step S916).”
A person in charge of layout creates, corrects and checks data in GDS format. In drawings, GDS data is used in the layout process (step S1201), and the EB data is used in the EB operation process (step S1202).
Since the dummy pattern for the area A is arranged in step S908, the amount of the GDS data increases in this process.
Associated with the increase of the amount of the GDS data, the time required to check the layout becomes large. Moreover, along with this, the area for storing the GDS data increases, so that the load of a process from the dummy pattern arrangement process (step S908) to step S913 becomes large.
That is, like the dummy pattern arrangement process (step S908) in FIGS. 12A and 12B, in a case where the dummy pattern creation on the area A is performed in the layout process (step S1201), it is required to hold data of the dummy pattern in the area A on the GDS data.
Therefore, a person in charge of layout has to deal with and manage a large amount of GDS data.
In Japanese Laid-Open Patent Application JP-P2003-324149A (referred to as the patent document 1), a technique for suppressing density variation by arranging dummy pattern is described. In this technique, the suppression of density variation is performed by arranging dummy patterns having various sizes, which is different from the above explained related techniques in which dummy patterns having same shape are arranged in a constant interval.
In above mentioned related techniques, dummy patterns only in the area A are created at a stage of layout formation in order to make the shapes of the dummy patterns being same to each other to arrange the dummy patterns on the area A. As a reference technique for explaining the present invention, this method is used in the following.